本书作者是功率半导体器件领域的著名专家，IGBT器件发明人之一。本书结合作者多年的实践经验，深入讨论了半导体功率器件的物理模型、工作原理、设计原则和应用特性，不仅详细介绍了硅基器件，还讨论了碳化硅器件的特性与设计要求。主要内容包括材料特性与输运物理、击穿电压、肖特基整流器、P-i-N整流器、功率MOSFET器件、双极型晶体管、晶闸管、IGBT器件等。 本书可作为微电子、电力电子等相关领域科研人员、工程技术人员的参考书，也可作为相关专业高年级本科生、研究生的教材。
样章试读
目录
- Preface
Chapter 1 Introduction
1.1 Ideal and Typical Power Switching Waveforms
1.2 Ideal and Typical Power Device Characteristics
1.3 Unipolar Power Devices
1.4 Bipolar Power Devices
1.5 MOS-Bipolar Power Devices
1.6 Ideal Drift Region for Unipolar Power Devices
1.7 Charge-Coupled Structures:Ideal Specific On-Resistance
1.8 Summary
Problems
References
Chapter 2 Material Properties and Transport Physics
2.1 Fundamental Properties
2.1.1 Intrinsic Carrier Concentration
2.1.2 Bandgap Narrowing
2.1.3 Built-in Potential
2.1.4 Zero-Bias Depletion Width
2.1.5 Impact Ionization Coefficients
2.1.6 Carrier Mobility
2.2 Resistivity
2.2.1 Intrinsic Resistivity
2.2.2 Extrinsic Resistivity
2.2.3 Neutron Transmutation Doping
2.3 Recombination Lifetime
2.3.1 Shockley-Read-Hall Recombination
2.3.2 Low-Level Lifetime
2.3.3 Space-Charge Generation Lifetime
2.3.4 Recombination Level Optimization
2.3.5 Lifetime Control
2.3.6 Auger Recombination
2.4 Ohmic Contacts
2.5 Summary
Problems
References
Chapter 3 Breakdown Voltage
3.1 Avalanche Breakdown
3.1.1 Power Law Approximations for the Impact Ionization Coefficients
3.1.2 Multiplication Coefficient
3.2 Abrupt One-Dimensional Diode
3.3 Ideal Specific On-Resistance
3.4 Abrupt Punch-Through Diode
3.5 Linearly Graded Junction Diode
3.6 Edge Terminations
3.6.1 Planar Junction Termination
3.6.2 Planar Junction with Floating Field Ring
3.6.3 Planar Junction with Multiple Floating Field Rings
3.6.4 Planar Junction with Field Plate
3.6.5 Planar Junction with Field Plates and Field Rings
3.6.6 Bevel Edge Terminations
3.6.7 Etch Terminations
3.6.8 Junction Termination Extension
3.7 Open-Base Transistor Breakdown
3.7.1 Composite Bevel Termination
3.7.2 Double-Positive Bevel Termination
3.8 Surface Passivation
3.9 Summary
Problems
References
Chapter 4 Schottky Rectifiers
4.1 Power Schottky Rectifier Structure
4.2 Metal-Semiconductor Contact
4.3 Forward Conduction
4.4 Reverse Blocking
4.4.1 Leakage Current
4.4.2 Schottky Barrier Lowering
4.4.3 Prebreakdown Avalanche Multiplication
4.4.4 Silicon Carbide Rectifiers
4.5 Device Capacitance
4.6 Thermal Considerations
4.7 Fundamental Tradeoff Analysis
4.8 Device Technology
4.9 Barrier Height Adjustment
4.10 Edge Terminations
4.11 Summary
Problems
References
Chapter 5 P-i-N Rectifiers
5.1 One-Dimensional Structure
5.1.1 Recombination Current
5.1.2 Low-Level Injection Current
5.1.3 High-Level Injection Current
5.1.4 Injection into the End Regions
5.1.5 Carrier-Carrier Scattering Effect
5.1.6 Auger Recombination Effect
5.1.7 Forward Conduction Characteristics
5.2 Silicon Carbide P-i-N Rectifiers
5.3 Reverse Blocking
5.4 Switching Performance
5.4.1 Forward Recovery
5.4.2 Reverse Recovery
5.5 P-i-N Rectifier Structure with Buffer Layer
5.6 Nonpunch-Through P-i-N Rectifier Structure
5.7 P-i-N Rectifier Tradeoff Curves
5.8 Summary
Problems
References
Chapter 6 Power MOSFETs
6.1 Ideal Specific On-Resistance
6.2 Device Cell Structure and Operation
6.2.1 The V-MOSFET Structure
6.2.2 The VD-MOSFET Structure
6.2.3 The U-MOSFET Structure
6.3 Basic Device Characteristics
6.4 Blocking Voltage
6.4.1 Impact of Edge Termination
6.4.2 Impact of Graded Doping Profile
6.4.3 Impact of Parasitic Bipolar Transistor
6.4.4 Impact of Cell Pitch
6.4.5 Impact of Gate Shape
6.4.6 Impact of Cell Surface Topology
6.5 Forward Conduction Characteristics
6.5.1 MOS Interface Physics
6.5.2 MOS Surface Charge Analysis
6.5.3 Maximum Depletion Width
6.5.4 Threshold Voltage
6.5.5 Channel Resistance
6.6 Power VD-MOSFET On-Resistance
6.6.1 Source Contact Resistance
6.6.2 Source Region Resistance
6.6.3 Channel Resistance
6.6.4 Accumulation Resistance
6.6.5 JFET Resistance
6.6.6 Drift Region Resistance
6.6.7 N^+ Substrate Resistance
6.6.8 Drain Contact Resistance
6.6.9 Total On-Resistance
6.7 Power VD-MOSFET Cell Optimization
6.7.1 Optimization of Gate Electrode Width
6.7.2 Impact of Breakdown Voltage
6.7.3 Impact of Design Rules
6.7.4 Impact of Cell Topology
6.8 Power U-MOSFET On-Resistance
6.8.1 Source Contact Resistance
6.8.2 Source Region Resistance
6.8.3 Channel Resistance
6.8.4 Accumulation Resistance
6.8.5 Drift Region Resistance
6.8.6 N^+ Substrate Resistance
6.8.7 Drain Contact Resistance
6.8.8 Total On-Resistance
6.9 Power U-MOSFET Cell Optimization
6.9.1 Orthogonal P-Base Contact Structure
6.9.2 Impact of Breakdown Voltage
6.9.3 Ruggedness Improvement
6.10 Square-Law Transfer Characteristics
6.11 Superlinear Transfer Characteristics
6.12 Output Characteristics
6.13 Device Capacitances
6.13.1 Basic MOS Capacitance
6.13.2 Power VD-MOSFET Structure Capacitances
6.13.3 Power U-MOSFET Structure Capacitances
6.13.4 Equivalent Circuit
6.14 Gate Charge
6.14.1 Charge Extraction
6.14.2 Voltage and Current Dependence
6.14.3 VD-MOSFET vs. U-MOSFET Structure
6.14.4 Impact of VD-MOSFET and U-MOSFET Cell Pitch
6.15 Optimization for High Frequency Operation
6.15.1 Input Switching Power Loss
6.15.2 Output Switching Power Loss
6.15.3 Gate Propagation Delay
6.16 Switching Characteristics
6.16.1 Turn-On Transient
6.16.2 Turn-Off Transient
6.16.3 Switching Power Losses
6.16.4 [dV/dt]Capability
6.17 Safe Operating Area
6.17.1 Bipolar Second Breakdown
6.17.2 MOS Second Breakdown
6.18 Integral Body Diode
6.18.1 Reverse Recovery Enhancement
6.18.2 Impact of Parasitic Bipolar Transistor
6.19 High-Temperature Characteristics
6.19.1 Threshold Voltage
6.19.2 On-Resistance
6.19.3 Saturation Transconductance
6.20 Complementary Devices
6.20.1 The p-Channel Structure
6.20.2 On-Resistance
6.20.3 Deep-Trench Structure
6.21 Silicon Power MOSFET Process Technology
6.21.1 Planar VD-MOSFET Process
6.21.2 Trench U-MOSFET Process
6.22 Silicon Carbide Devices
6.22.1 The Baliga-Pair Configuration
6.22.2 Planar Power MOSFET Structure
6.22.3 Shielded Planar Power MOSFET Structures
6.22.4 Shielded Trench-Gate Power MOSFET Structure
6.23 Summary
Problems
References
Chapter 7 Bipolar Junction Transistors
7.1 Power Bipolar Junction Transistor Structure
7.2 Basic Operating Principles
7.3 Static Blocking Characteristics
7.3.1 Open-Emitter Breakdown Voltage
7.3.2 Open-Base Breakdown Voltage
7.3.3 Shorted Base-Emitter Operation
7.4 Current Gain
7.4.1 Emitter Injection Efficiency
7.4.2 Emitter Injection Efficiency with Recombination in the Depletion Region
7.4.3 Emitter Injection Efficiency with High-Level Injection in the Base
7.4.4 Base Transport Factor
7.4.5 Base Widening at High Collector Current Density
7.5 Emitter Current Crowding
7.5.1 Low-Level Injection in the Base
7.5.2 High-Level Injection in the Base
7.5.3 Emitter Geometry
7.6 Output Characteristics
7.7 On-State Characteristics
7.7.1 Saturation Region
7.7.2 Quasisaturation Region
7.8 Switching Characteristics
7.8.1 Turn-On Transition
7.8.2 Turn-Off Transition
7.9 Safe Operating Area
7.9.1 Forward-Biased Second Breakdown
7.9.2 Reverse-Biased Second Breakdown
7.9.3 Boundary for Safe Operating Area
7.10 Darlington Configuration
7.11 Summary
Problems
References
Chapter 8 Thyristors
8.1 Power Thyristor Structure and Operation
8.2 Blocking Characteristics
8.2.1 Reverse-Blocking Capability
8.2.2 Forward-Blocking Capability
8.2.3 Cathode Shorting
8.2.4 Cathode Shorting Geometry
8.3 On-State Characteristics
8.3.1 On-State Operation
8.3.2 Gate-Triggering Current
8.3.3 Holding Current
8.4 Switching Characteristics
8.4.1 Turn-On Time
8.4.2 Gate Design
8.4.3 Amplifying Gate Design
8.4.4 [dV/dt]Capability
8.4.5 Turn-Off Process
8.5 Light-Activated Thyristors
8.5.1 [dI/dt]Capability
8.5.2 Gate Region Design
8.5.3 Optically Generated Current Density
8.5.4 Amplifying Gate Design
8.6 Self-Protected Thyristors
8.6.1 Forward Breakdown Protection
8.6.2 [dV/dt]Turn-On Protection
8.7 The Gate Turn-Off Thyristor Structure
8.7.1 Basic Structure and Operation
8.7.2 One-Dimensional Turn-Off Criterion
8.7.3 One-Dimensional Storage Time Analysis
8.7.4 Two-Dimensional Storage Time Model
8.7.5 One-Dimensional Voltage Rise Time Model
8.7.6 One-Dimensional Current Fall Time Model
8.7.7 Switching Energy Loss
8.7.8 Maximum Turn-Off Current
8.7.9 Cell Design and Layout
8.8 The Triac Structure
8.8.1 Basic Structure and Operation
8.8.2 Gate-Triggering Mode 1
8.8.3 Gate-Triggering Mode 2
8.8.4 [dV/dt]Capability
8.9 Summary
Problems
References
Chapter 9 Insulated Gate Bipolar Transistors
9.1 Basic Device Structures
9.2 Device Operation and Output Characteristics
9.3 Device Equivalent Circuit
9.4 Blocking Characteristics
9.4.1 Symmetric Structure Forward-Blocking Capability
9.4.2 Symmetric Structure Reverse-Blocking Capability
9.4.3 Symmetric Structure Leakage Current
9.4.4 Asymmetric Structure Forward-Blocking Capability
9.4.5 Asymmetric Structure Reverse-Blocking Capability
9.4.6 Asymmetric Structure Leakage Current
9.5 On-State Characteristics
9.5.1 On-State Model
9.5.2 On-State Carrier Distribution:Symmetric Structure
9.5.3 On-State Voltage Drop:Symmetric Structure
9.5.4 On-State Carrier Distribution:Asymmetric Structure
9.5.5 On-State Voltage Drop:Asymmetric Structure
9.5.6 On-State Carrier Distribution:Transparent Emitter Structure
9.5.7 On-State Voltage Drop:Transparent Emitter Structure
9.6 Current Saturation Model
9.6.1 Carrier Distribution:Symmetric Structure
9.6.2 Output Characteristics:Symmetric Structure
9.6.3 Output Resistance:Symmetric Structure
9.6.4 Carrier Distribution:Asymmetric Structure
9.6.5 Output Characteristics:Asymmetric Structure
9.6.6 Output Resistance:Asymmetric Structure
9.6.7 Carrier Distribution:Transparent Emitter Structure
9.6.8 Output Characteristics:Transparent Emitter Structure
9.6.9 Output Resistance:Transparent Emitter Structure
9.7 Switching Characteristics
9.7.1 Turn-On Physics:Forward Recovery
9.7.2 Turn-Off Physics:No-Load Conditions
9.7.3 Turn-Off Physics:Resistive Load
9.7.4 Turn-Off Physics:Inductive Load
9.7.5 Energy Loss per Cycle
9.8 Power Loss Optimization
9.8.1 Symmetric Structure
9.8.2 Asymmetric Structure
9.8.3 Transparent Emitter Structure
9.8.4 Comparison of Tradeoff Curves
9.9 Complementary(P-Channel)Structure
9.9.1 On-State Characteristics
9.9.2 Switching Characteristics
9.9.3 Power Loss Optimization
9.10 Latch-Up Suppression
9.10.1 Deep P^+ Diffusion
9.10.2 Shallow P^+ Layer
9.10.3 Reduced Gate Oxide Thickness
9.10.4 Bipolar Current Bypass
9.10.5 Diverter Structure
9.10.6 Cell Topology
9.10.7 Latch-Up Proof Structure
9.11 Safe Operating Area
9.11.1 Forward-Biased Safe Operating Area
9.11.2 Reverse-Biased Safe Operating Area
9.11.3 Short-Circuit Safe Operating Area
9.12 Trench-Gate Structure
9.12.1 Blocking Mode
9.12.2 On-State Carrier Distribution
9.12.3 On-State Voltage Drop
9.12.4 Switching Characteristics
9.12.5 Safe Operating Area
9.12.6 Modified Structures
9.13 Blocking Voltage Scaling
9.13.1 N-Base Design
9.13.2 Power MOSFET Baseline
9.13.3 On-State Characteristics
9.13.4 Tradeoff Curve
9.14 High Temperature Operation
9.14.1 On-State Characteristics
9.14.2 Latch-Up Characteristics
9.15 Lifetime Control Techniques
9.15.1 Electron Irradiation
9.15.2 Neutron Irradiation
9.15.3 Helium Irradiation
9.16 Cell Optimization
9.16.1 Planar-Gate Structure
9.16.2 Trench-Gate Structure
9.17 Reverse Conducting Structure
9.18 Summary
Problems
References
Chapter 10 Synopsis
10.1 Typical H-Bridge Topology
10.2 Power Loss Analysis
10.3 Low DC Bus Voltage Applications
10.4 Medium DC Bus Voltage Applications
10.5 High DC Bus Voltage Applications
10.6 Summary
Problems
References
Index
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