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  60GHz CM...
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　　The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. However，challenges related to circuit，layout and measurements during mm-wave CMOS IC design have to be overcome before they can become viable for mass market. 60 GHz CMOS Phase-Locked Loops focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL，along with separate implementations of individual components such as voltage controlled oscillators，injection locked frequency dividers and their combinations，are included. Furthermore，to satisfy a number of transceiver topologies simultaneously，flexibility is introduced in the PLL architecture by using new dual-mode ILFDs and switchable VCOs，while reusing the low frequency components at the same time.

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• 
  2 Synthesizer System Architecture
  
  2.1 IEEE 802.15.3c Channelization
  
  2.2 60 GHz Frequency Conversion Techniques
  
  2.3 Proposed PLL Architecture: F1exible, Reusable,Mu1ti-frequency
  
  2.3.1 Utilization in WiComm Project
  
  2.4 System Analysis and Design
  
  2.4.1 Phase-Lock Lοop Basics
  
  2.4.2 Frequency Planning
  
  2.4.3 Synthesizer Parameters
  
  2.5 System Simulations
  
  2.6 Target Specifications
  
  2.7 Summary
  
  3 Layout and Measurements at mm-Wave Frequencies
  
  3.1 Layout Problems and Solutions
  
  3.1.1 Impact of Parasitics
  
  3.1.2 Mismatch Due to Layout Asymmetry and Device Orientation
  
  3.1.3 Substrate Losses
  
  3.1.4 Cross Talk Shielding and Grounding
  
  3.2 Measurement Setups
  
  3.2.1 Dedicated Instrurnentation
  
  3.2.2 Ca1ibration and De-embedding
  
  3.2.3 Stability and Repeatability
  
  3.3 Conclusions
  
  4 Design of High Frequency Components
  
  4.1 Presca1er
  
  4.1.1 Overview and Comparison of Presca1er Architectures
  
  4.1.2 35 GHz Static Frequency Divider
  
  4.1.3 40 GHz Divide-by-2 ILFD
  
  4.1.4 60 GHz Divide-by-3 ILFD
  
  4.1.5 Monolithic Transformer Design and Measurement
  
  4.1.6 Dua1-Mode(Divide-by-2 and Divide-by-3) LLFD
  
  4.1.7 ILFD fìgure-of-Merit(FOM)
  
  4.1.8 Summary
  
  4.2 Vo1tage Controlled Oscillator
  
  4.2.1 Overview of VCO Architectures
  
  4.2.2 Theoretica1 Ana1ysis of LC-VCOs
  
  4.2.3 40 GHz LC VCO
  
  4.2.4 60 GHz Active1y Coup1ed I-Q VCO
  
  4.2.5 60 GHz Transformer Coup1ed I-Q VCO
  
  4.2.6 Dua1-Band VCO for 40 and 60 GHz
  
  4.3 Synthesizer Front-Ends
  
  4.3.1 40 GHz VCO and Divide-by-2 ILFD
  
  4.3.2 60 GHz VCO and Divide-by-3 ILFD
  
  4.4 Conc1usions
  
  5 Design of Low Frequency Components
  
  5.1 Feedback Division
  
  5.1.1 CML Based Divider Chain
  
  5.1.2 Mixer Based Division
  
  5.2 Phase-Frequency Detector,Charge-Pump and Loop Fi1ter
  
  5.3 Conc1usions
  
  6 Synthesizer Integration
  
  6.1 Synthesizer for 60 GHz Sliding-IF Frequency Conversion
  
  6.1.1 Comparison to Target Specifìcations
  
  6.2 Synthesizer with Down-Conversion Mixer in Feedback Loop
  
  6.3 Dual-Mode Synthesizer
  
  6.4 Conclusions
  
  7 Conclusions
  
  Appendix
  
  Appendix A
  
  A Travelling Wave Divider Simulation Results
  
  Appendix B
  
  B LC-VCOs Theory
  
  References]]>