本书针对在SOC芯片上使用的全集成频率合成器的设计，从电路和系统的角度对锁相环的原理和设计进行了分析。特别是在电路层次上，讨论了深亚微米CMOS数字工艺中的低电压模拟电路的设计，有比较大的参考意义。在对锁相环基本工作原理分析的基础之上，本书分析了具体的时钟产生方案和电路设计问题，并进一步讨论了锁相环的应用。本书还包括了PLL可测试性设计的内容。最后还从宏观角度讨论了SOC时钟域的设计。书中包含的大量实际问题分析应该有助于读者更好地理解时钟产生器设计中的核心问题。
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目录
- ABOUT THE AUTHOR
PREFACE
FOREWORD
1.INTRODUCTION
1.1 WHAT ARE SYSTEM-ON-A-CHIP PROCESSORS?
1.2 ORGANIZATION
2.PHASE-LOCKED LOOP FUNDAMENTALS
2.1 Introduction
2.2 PLL Basics
2.2.1 PLL Specincations
2.2.2 Charge Pump PLLs
2.2.3 PLL Building Blocks
2.3 Continuous-time Linear Analysis of PLLs
2.4 Discrete-time Linear Analysis of PLLs
2.5 Nonlinear Locking Behaviour of PLLs
2.6 Summary
3.LOW-VOLTAGE ANALOG CMOS DESIGN
3.1 Introduction
3.2 MOS Transistors
3.3 Low-Voltage Current Mirrors
3.4 Low-Voltage Charge Pumps
3.5 Low-Voltage Oscillator Design
3.5.1 Digital Tuning Circuitry
3.5.2 Ring Oscillator Design
3.5.3 LC VCO Design
3.6 Voltage and Current References
3.7 Summary
4.JITTER ANALYSIS IN PHASE-LOCKED LOOPS
4.1 Introduction
4.2 Jitter Basics
4.2.1 Definition of Jitter
4.2.2 Sources of Jitter
4.2.3 Jitter and Phase Noise
4.3 Jitter in Voltage Controlled Oscillators
4.3.1 Classical Phase Noise Analysis
4.3.2 Cyclostationary Phase Noise Analysis
4.3.3 CMOS Voltage Controlled Ring Oscillators
4.3.4 Jitter in Differential LC VCOs
4.4 Jitter Performance of Closed-Loop PLL System
4.4.1 Basic Linear Analysis
4.4.2 Effect of Varving Loop Parameters
4.4.3 Effect of PFD Nonlinearities on Jitter
4.5 Coupling Noise Effects on Jitter
4.5.1 Power Supply Coupling Noise
4.5.2 Substrate Coupling Noise
4.6 Summary
5.LOW-JITTER PLL ARCHITECTURES
5.1 Introduction
5.2 Differential PLL Architecture
5.2.1 Conventional Topology
5.2.2 Low-Noise Difierential PLL Topology
5.3 Supply Voltage Regulated PLL Architectures
5.3.1 Basic Concept
5.3.2 Regulator Topologies
5.3.2.1 Linear Voltage Regulator
5.3.2.2 Source Follower Voltage Regulator
5.3.2.3 Hybrid Voltage Regulation Approach
5.3.3 Performance Comparison
5.4 Adaptive PLL Archiectures
5.4.1 Two-Mode Bandwidth Architecture
5.4.2 Process Insensitive Design
5.4.3 Analog Loop Bandwidth Controller
5.5 Resistorless Loop Filter PLLs
5.5.1 Basic Concept
5.5.2 Sample-Reset Loop Filter
5.6 Delay-Locked Loop Freguency Multipliers
5.6.1 DLL Operating Principle
5.6.2 DLL as a Frequency Synthesizer
5.6.3 Jitter Analysis
5.6.4 Hybrid PLL／DLL Approach
5.7 Summary
6.DIGITAL PLL DESICN
6.1 Introduction
6.2 Basic Topology
6.3 Z-domain Analysis
6.3.1 Linear Model of DPLL
6.3.2 Linesr Performance Evaluation
6.4 Circuit Implementation Issues
6.4.1 DAC optimization
6.4.2 Reference current temperature stability
6.4.3 Experimental Results
6.5 Alternate Digital PLL for Clock Generation
6.5.1 All-Digital PLL for Digitally Controlled Oscillator
6.5.2 A11-Digital FLL with Phase Reset
6.6 Summary
7.DSP CLOCK CENERATOR ARCHITECTURES
7.1 Introduction
7.1.1 Why important?
7.1.2 Typical DSP Clock Generation Specifications
7.2 Sampling Clock Requirements for Data Converters
7.2.1 First order Analysis
7.2.2 General Case-A Qualitative Approach
7.2.3 General Case-A Quantitative Approach
7.2.4 Specific Case-Sigma-Delta A/D Converters
7.3 Jitter in Frequency Dividers
7.3.1 Uses of Frequency Dividors in SoC Processors
7.3.2 Mechanism of Jitter in digital frequency dividers
7.3.3 Synchronous Divider Model
7.3.4 Asynchronous Divider Model
7.3.5 Results
7.4 Fractional-N PLLs as Clock Generators
7.4.1 Basic Toplogy
7.4.2 Sigma-Delta PLLs
7.4.2.1 Basic Operation
7.4.2.2 Sigma-Delta Dithering
7.5 Oversampled PLL Topologies
7.6 Direct Digital Synthesis with Analog lnterpolation
7.6.1 MNA Concept and Architecture
7.6.2 Parameter Analysis of MNA Counter
7.6.3 Circuit Implementation
7.6.4 Results
7.7 Summary
8.DESlGN FOR TESTABILITY IN PLLS
8.1 Introduction
8.2 Verification of SoC PLLs
8.2.1 Overview
8.2.2 Required PLL Tests
8.3 Jitter Measurement Techniques
8.3.1 High-Bandwidth ATE Jitter Measurement Setup
8.3.2 ATE Jitter Test Equipment
8.4 Design for Testability and Self-Test in PLLs
8.4.1 Functional Test
8.4.2 Indirect Jitter Measurement Techniques
8.4.3 Precise On-Chip Jitter Measurement
8.5 Summary
9.CLOCK PARTITIONING AND SKEW CONTROL
9.1 Introduction
9.2 Clock Distribution Networks in SoCs
9.3 Performance Limitations in Clock Networks
9.4 Active Skew Management Strategies
9.4.1 Effect of Clock Skew, Jitter on Power Consumption
9.4.2 Ad-hoc Deskew Strategies
9.4.3 DLL-based Deskew Strategies
9.5 Multi-phase Clock Generator
9.5.1 Passive Method
9.5.2 Master-Slave DLL
9.5.3 Pulsewidth Control Loops
9.6 Low-Power Clock Distribution Strategies
9.6.1 Active Clock Gating
9.6.2 Low-Power Gigahertz Clock Strategies
9.7 Multi-clock Domain Interfacing
9.8 Summary
INDEX
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